UART in VHDL giving CoolTerm a framing error
I am not very adept at VHDL.
I am trying to make a UART with 9600 BAUD 8-n-1
in VHDL. I am currently receiving a framing error and crash from CoolTerm when trying to communicate through USB.
I tried changing the number of bits in the array to 9 and setting the done bit in the idle state only. It still give me the error.
Transfer : process (Start_Tx, Osc, Value) is
variable Count : integer range 0 to 10416 ; -- Baud rate is calculated by OSC/Baud giving 10417 cycles
variable Iterator : integer range 0 to 9 ; -- The iteration variable to control which bit is shown
begin
if rising_edge(Osc) then -- on a rising edge
case (Current_State) is -- determine the current state
when IDLE =>
-- During the idle state the TX line should be held high, the done bit is also idle high
Tx_Out <= '1';
Tx_Done <= '1';
-- Start TX is a button input that when pressed will start the transfer
if(Start_Tx = '1')
then Current_State <= TRANSMIT ;
Tx_Done <= '0';
else Current_State <= IDLE;
end if;
when TRANSMIT =>
-- the transfer array is used to hold the values to be TX ( currently holding a dummy value for testing)
-- the value is as follows 'Start bit' "00010010" transfer data 'Stop Bit'
Transfer_Array <= "0000100101";
-- Transfer out starts with a value of Transfer_Array(0)
-- and will be iterated through every 10417 cycles for 9600 Baud
Tx_Out <= Transfer_Array(Iterator); -- Show digit
-- if the count is full Reset and check/ increment the Iterator and change states
-- if not increment the counter
if (Count = 10416)
then Count := 0 ;
if (Iterator = 9)
then Iterator := 0 ;
Current_State <= IDLE;
else Current_State <= TRANSMIT;
Iterator := Iterator +1;
end if;
else Count := Count + 1 ;
end if;
end case;
end if;
end process;
end Behavioral;
serial-port vhdl fpga uart baud-rate
add a comment |
I am not very adept at VHDL.
I am trying to make a UART with 9600 BAUD 8-n-1
in VHDL. I am currently receiving a framing error and crash from CoolTerm when trying to communicate through USB.
I tried changing the number of bits in the array to 9 and setting the done bit in the idle state only. It still give me the error.
Transfer : process (Start_Tx, Osc, Value) is
variable Count : integer range 0 to 10416 ; -- Baud rate is calculated by OSC/Baud giving 10417 cycles
variable Iterator : integer range 0 to 9 ; -- The iteration variable to control which bit is shown
begin
if rising_edge(Osc) then -- on a rising edge
case (Current_State) is -- determine the current state
when IDLE =>
-- During the idle state the TX line should be held high, the done bit is also idle high
Tx_Out <= '1';
Tx_Done <= '1';
-- Start TX is a button input that when pressed will start the transfer
if(Start_Tx = '1')
then Current_State <= TRANSMIT ;
Tx_Done <= '0';
else Current_State <= IDLE;
end if;
when TRANSMIT =>
-- the transfer array is used to hold the values to be TX ( currently holding a dummy value for testing)
-- the value is as follows 'Start bit' "00010010" transfer data 'Stop Bit'
Transfer_Array <= "0000100101";
-- Transfer out starts with a value of Transfer_Array(0)
-- and will be iterated through every 10417 cycles for 9600 Baud
Tx_Out <= Transfer_Array(Iterator); -- Show digit
-- if the count is full Reset and check/ increment the Iterator and change states
-- if not increment the counter
if (Count = 10416)
then Count := 0 ;
if (Iterator = 9)
then Iterator := 0 ;
Current_State <= IDLE;
else Current_State <= TRANSMIT;
Iterator := Iterator +1;
end if;
else Count := Count + 1 ;
end if;
end case;
end if;
end process;
end Behavioral;
serial-port vhdl fpga uart baud-rate
Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27
add a comment |
I am not very adept at VHDL.
I am trying to make a UART with 9600 BAUD 8-n-1
in VHDL. I am currently receiving a framing error and crash from CoolTerm when trying to communicate through USB.
I tried changing the number of bits in the array to 9 and setting the done bit in the idle state only. It still give me the error.
Transfer : process (Start_Tx, Osc, Value) is
variable Count : integer range 0 to 10416 ; -- Baud rate is calculated by OSC/Baud giving 10417 cycles
variable Iterator : integer range 0 to 9 ; -- The iteration variable to control which bit is shown
begin
if rising_edge(Osc) then -- on a rising edge
case (Current_State) is -- determine the current state
when IDLE =>
-- During the idle state the TX line should be held high, the done bit is also idle high
Tx_Out <= '1';
Tx_Done <= '1';
-- Start TX is a button input that when pressed will start the transfer
if(Start_Tx = '1')
then Current_State <= TRANSMIT ;
Tx_Done <= '0';
else Current_State <= IDLE;
end if;
when TRANSMIT =>
-- the transfer array is used to hold the values to be TX ( currently holding a dummy value for testing)
-- the value is as follows 'Start bit' "00010010" transfer data 'Stop Bit'
Transfer_Array <= "0000100101";
-- Transfer out starts with a value of Transfer_Array(0)
-- and will be iterated through every 10417 cycles for 9600 Baud
Tx_Out <= Transfer_Array(Iterator); -- Show digit
-- if the count is full Reset and check/ increment the Iterator and change states
-- if not increment the counter
if (Count = 10416)
then Count := 0 ;
if (Iterator = 9)
then Iterator := 0 ;
Current_State <= IDLE;
else Current_State <= TRANSMIT;
Iterator := Iterator +1;
end if;
else Count := Count + 1 ;
end if;
end case;
end if;
end process;
end Behavioral;
serial-port vhdl fpga uart baud-rate
I am not very adept at VHDL.
I am trying to make a UART with 9600 BAUD 8-n-1
in VHDL. I am currently receiving a framing error and crash from CoolTerm when trying to communicate through USB.
I tried changing the number of bits in the array to 9 and setting the done bit in the idle state only. It still give me the error.
Transfer : process (Start_Tx, Osc, Value) is
variable Count : integer range 0 to 10416 ; -- Baud rate is calculated by OSC/Baud giving 10417 cycles
variable Iterator : integer range 0 to 9 ; -- The iteration variable to control which bit is shown
begin
if rising_edge(Osc) then -- on a rising edge
case (Current_State) is -- determine the current state
when IDLE =>
-- During the idle state the TX line should be held high, the done bit is also idle high
Tx_Out <= '1';
Tx_Done <= '1';
-- Start TX is a button input that when pressed will start the transfer
if(Start_Tx = '1')
then Current_State <= TRANSMIT ;
Tx_Done <= '0';
else Current_State <= IDLE;
end if;
when TRANSMIT =>
-- the transfer array is used to hold the values to be TX ( currently holding a dummy value for testing)
-- the value is as follows 'Start bit' "00010010" transfer data 'Stop Bit'
Transfer_Array <= "0000100101";
-- Transfer out starts with a value of Transfer_Array(0)
-- and will be iterated through every 10417 cycles for 9600 Baud
Tx_Out <= Transfer_Array(Iterator); -- Show digit
-- if the count is full Reset and check/ increment the Iterator and change states
-- if not increment the counter
if (Count = 10416)
then Count := 0 ;
if (Iterator = 9)
then Iterator := 0 ;
Current_State <= IDLE;
else Current_State <= TRANSMIT;
Iterator := Iterator +1;
end if;
else Count := Count + 1 ;
end if;
end case;
end if;
end process;
end Behavioral;
serial-port vhdl fpga uart baud-rate
serial-port vhdl fpga uart baud-rate
edited Nov 23 '18 at 12:52
Stoogy
647622
647622
asked Nov 23 '18 at 5:53
bryantbryant
41
41
Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27
add a comment |
Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27
Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27
Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27
add a comment |
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Could you give the error message from CoolTerm ?
– Stoogy
Nov 23 '18 at 11:27